This invention relates to a multi-level nonvolatile semiconductor memory device, and more particularly to a multi-level nonvolatile semiconductor memory device in which multi-level information is written into a memory cell in a plurality of write-phases and the verify operation for written data is effected in order to precisely control the threshold voltage distribution in the written state of the memory cell for each write-phase.
Conventionally, the write and read operations for the multi-level nonvolatile semiconductor memory device having four memory states in one memory cell are effected as follows.
In a memory cell transistor having a floating gate structure, the threshold voltage thereof is shifted to one of four regions shown in FIG. 1 by controlling the number of electrons injected into the floating gate by use of the control gate formed above the floating gate at the write time.
The memory states are defined such that the regions of the threshold voltage Vth of the memory cell transistor of Vth .ltoreq.-2.0V, 0.4V.ltoreq.Vth.ltoreq.0.8V, 1.6V.ltoreq.Vth.ltoreq.2.0V and 2.8V.ltoreq.Vth.ltoreq.3.2V are respectively represented by two bits of "11", "10", "01" and "00". Further, 0V, 1.2V and 2.4V indicated on the abscissa of FIG. 1 are voltages applied to the word line when "10", "01" and "00" are read out.
One example of a sense/latch circuit of the conventional four-level nonvolatile semiconductor memory device including NAND-type flash memory cells is shown in FIG. 2. The circuit is disclosed in ISSCC 1996 digest of Technical Papers, vol. 31, pp. 32-33.
A memory cell array 1 includes NAND-type cells each including a plurality of serially connected memory cells having the floating gate structure. In this case, a series circuit of memory cells MC0 to MC15 is connected at one end to a bit line BL1 via a drain side selection transistor S1 and connected at the other end to a preset power supply terminal (which is normally grounded) which is indicated by an arrow via a source side selection transistor S2.
WL0 to WL15 are word lines, and SGD, SGS are drain side and source side selection lines. Sense amplifiers each having a first latch circuit 10 and second latch circuit 11 for holding four-level information are arranged one for every two bit lines. In the following description, the first latch circuit 10 is referred to as LATCH1, the second latch circuit 11 is referred to as LATCH2, and the sense amplifier including LATCH1 and LATCH2 is referred as a sense/latch circuit.
In a NAND-type flash memory, the threshold voltages of unselected memory cells serially connected to the selected memory cell at the readout operation, for example, are set to be lower than the word line voltage and the unselected memory cells must be set in the ON-state.
Further, since the data write operation, the verify operation for the write state (which is hereinafter simply referred to as "verify"), and the readout operation for the multi-level nonvolatile semiconductor memory device are effected for each page unit, data of one page is temporarily held in the sense amplifiers including the data-latch circuits at the write time, the data is output to the bit lines and the write voltage is applied to the word lines so as to write data into the memory cells, and at the readout time, the readout voltage is applied to the word lines and information items read out to the bit lines are fetched into the sense amplifiers having the data-latch circuits.
Conventionally, in the write and read operations, an example of the voltages of the selection lines and the word lines of the memory cell array is shown in TABLE 1.
TABLE 1 ______________________________________ WRITE READ ______________________________________ SDG Vcc 6 V WLi - 1 0 V 6 V WLi (SELECTED) 20 V 2.4/1.2/0 V WLi + 1 0 V 6 V WL (OTHERS) 11 V 6 V SGS 0 V 6 V ______________________________________
WLi-1, WLi (SELECTED), WLi+1 indicate the voltages of a selected word line and neighboring word lines. A midlevel voltage of 11V is applied to the unselected word lines which are different from the above word lines and the above neighboring word lines are applied with a word line voltage 0V for setting the channel into the electrically floating state for local self-boosting of the channel of the selected memory cell. The selected word line is applied with a write voltage 20V.
If a write method by self boosting is used, the voltage amplitude from the write voltage 0V to approx. 10V (write-inhibit midlevel voltage) supplied to the bit line at the write time in the normal fixed voltage write method can be lowered to the voltage amplitude from 0V to 3.3V (Vcc) and the midlevel voltage generation circuit for bit line voltage can be omitted.
The write method by self boosting is described in detail in K. D. Suh et al., IEEE Journal of Solid State Circuits, vol. 30, No. 11, pp. 1149-1156 (1995) and the write method by local self boosting is described in detail in T. S. Jung et al., ISSCC 1996 Digest of Technical Papers, p. 32.
Next, the write and verify operations of the conventional four-level nonvolatile semiconductor memory device are specifically explained with reference to FIGS. 2 and 3. FIG. 3 is a timing diagram for illustrating the write and verify operations of the circuit of FIG. 2.
DECOUPLE in FIG. 2 indicates a control line for separating the memory cell array 1 so as to prevent the voltage at the erase time from influencing the sense/latch circuit at the erase time for the memory cell and controlling the voltage to enhance the speed of the sensing operation. In the following description, the operation of DECOUPLE is not particularly described since it is not directly related to this invention.
The sense/latch circuit 2 includes LATCH1 and LATCH2 surrounded by broken lines 10, 11. INH1, INH2 are inhibit signals for supplying Vcc to the bit lines at the write time, and Vref is a reference voltage used for readout or the like. Vref is applied to the gate of the transistor which operates as a precharge transistor at the readout time according to whether the precharged voltage to the bit line is discharged or maintained. A1, A2 are address signals of the bit lines, RESET is a reset signal, and PGM1 PGM2 are program signals supplied in the write operation sequence for the four-level data.
Further, N1 is a node for connecting the connection nodes of the address signal input transistors and the program signal input transistors which are respectively connected in series with the bit lines BL1, BL2 and the node is hereinafter referred to as N1 or node one. The drain of the reset transistor is also connected to N1. L1, L2, L3 are read signals used for reading out information written into the memory cell to LATCH1, LATCH2 and 3 indicates a column decoder.
In the circuit of FIG. 2, the arrows are normally grounded but may be connected to a preset power supply terminal (this is also applied to FIG. 6 and FIGS. 9 to 11).
As described before, in order to write data into the memory cell, approx. 20V is applied to the control gate and 0V is applied to the channel of the substrate surface to inject electrons into the floating gate which lies below the control gate by the tunneling phenomenon. The voltage of the channel of the substrate surface of the non-write cell which commonly has a word line with the write cell is set to approx. 10V so that the probability of occurrence of the above tunneling phenomenon will be significantly reduced and thus the data writing can be inhibited.
Using the self boosting for boosting the power supply voltage vcc supplied from the bit line, the channel voltage is boosted to approx. 10V by setting the channel into the electrically floating state, dividing the voltage applied to the control gate by capacitance division by use of the inter-electrode capacitance of the memory cell. Therefore, it is understood that the bit line voltage for the write inhibited cell may be set to Vcc.
In order to give four-level memory states to a memory cell, as shown in FIG. 3, the threshold value of the cell is controlled in three stages of "10" program, "01" program and "00" program. First, four-level data is written into the memory cell on the bit line BL1 selected by the address signal A1.
At the write time, write information is supplied to LATCH1, LATCH2 as 2-bit data (Q2, Q1) according to the definition of FIG. 1. Q1, Q2 are voltage levels of the nodes of the latch circuit at which LATCH1 and LATCH2 shown in FIG. 2 are connected to the respective bit lines. That is, "10" data is loaded in the latch circuit as Q1: L and Q2: H, "01" data is loaded in the latch circuit as Q1: H and Q2: L, and "00" data is loaded in the latch circuit as Q1: L and Q2: L.
The write operation is effected for each page unit and the verify operation is effected for each bit. In this conventional case, the verify operation is effected by detecting the current in the bit line after the write operation. In addition, a method for judging data based on whether or not the precharge voltage of the bit line is maintained is provided.
In the "10" program of FIG. 3, A2 is first set to "L", INH2 is set to "H" to separate the bit line BL2, and information of the lower bit Q1 is transferred to the bit line BL1 with PGM1 and the address signal A1 set at "H". At this time, if Q1 is "L", the bit line is normally grounded.
After this, the write voltage 20V is applied to the selected word line for a preset period of time as shown by WL in FIG. 3, then the voltage of WL is returned to the verify voltage 0.4V of "10" data and the program-verify operation is effected.
If the threshold voltage of the memory cell exceeds 0.4V by the write voltage, the memory cell is set into the OFF state. Therefore, no current flows in the bit line and the bit line voltage is applied to M1 and "H" of Q2 is input to M2 so that the inverted node Q1B of Q1 will be grounded via M1, M2, M3 by supplying a read signal L1 to M3, and as shown by an arrow in FIG. 3, Q1 is inverted to "H". At this time, "L" of Q1 in "00" data is cut OFF by M2 since Q2 is "L" and it will not inverted to "1".
In this case, L1 is used as a signal for verifying the write state, but as described before, since the verify operation is also effected by reading out the write state to the latch circuit, L1 is referred to as the read signal in the verify operation in the following description. This is also applied to L2, L3.
Further, the connection node Q1 of LATCH1 connected to BL1 via a plurality of serially connected transistors is referred to as one of the nodes of LATCH1 and Q1B is referred to as the inverted node of LATCH1. This is also applied to Q2, Q2B.
The "10" program is Terminated after a sequence of write and verify operations are repeated by a number n (n is a natural number of n.gtoreq.1) of times until "10" data is normally written to all the memory cells into which "10" data is to be written. Since the write operation is inhibited if Q1 is "H" at the write time, the write operation is effected only in the case of "00" and "10" in the "10" program.
If data is "10" in the above case and the threshold value of the memory cell becomes equal to or higher than 0.4V in the i-th (i is a natural number of n.gtoreq.i.gtoreq.1) write operation, Q1 is inverted to "H" when M3 is turned ON and the (i+1)-th and succeeding write operations are inhibited.
However, since Q1 is not inverted to "H" unlike the above case if data is "00", the write operation is repeated by n times until the "10" program is terminated.
Next, "L" of Q2 of LATCH2 is transferred to the bit line BL1 by PGM2 and A1 in the "01" program and the write voltage 20V is applied to the word line WL of the memory cell for a preset period of time so as to effect the write operation. Then, the voltage of WL is returned to the verify voltage 1.6V of the "01" data and the program-verify operation is effected. If the threshold value of the memory cell exceeds 1.6V, no detection current flows, the inverted node Q2B of Q2 is grounded by M4 which is applied with the detection voltage and M5 which is supplied with the read signal L2, and as shown by two arrows shown in FIG. 3, Q2 is inverted to "H". At the same time, Q2 of the "00" data is also inverted to "H" as indicated by the two arrows.
Finally, if the threshold voltage of the memory cell exceeds 2.8V in the "00" program, Q1 of the "00" data is inverted to "H" by the read signal Li as indicated by the arrow of FIG. 3. The write operation effected in the "00" program is effected only for the memory cell into which "00" data is written. Thus, after the respective programs of "10", "01", "00" are effected, all of Q1, Q2 giving four-level data are inverted to "H" and it is verified that four-level data written into the memory cell is not insufficiently written. However, in the conventional write and verify operations explained here, an unpreferable write operation is repeated for the memory cell into which "00" data is written at the same time that "10" data is written in the "10" program as described before, and over-program of "00" data may occur.
Next, the readout operation of four-level data is explained. Readout of data to LATCH1, LATCH2 is effected in three divided phases as shown in FIG. 4. Prior to the readout operation, the RESET signal, PGM1, PGM2 signals are set to "H" and all of the nodes Q1, Q2 are set to "L" so as to reset LATCH1, LATCH2. In the readout operation, L1 is set to "L".
In the phase1, the lower bit Q1 of "00" data written in the memory cell is read out. The word line connected to the control gate of the memory cell is set to 2.4V. If the threshold value of the memory cell is equal to or higher than 2.4V, that is, it is included in the distribution of "00" shown in FIG. 1, the memory cell in which "00" data is written is set in the OFF state, no current flows in the bit line and a voltage is detected, but a current flows in the bit line and it is grounded in the case of the other write data.
The bit line voltage is applied to the transistor M1 and fetched into LATCH1 by the read signal L3 which is input to M20, but at this time, the readout operation is controlled by Q2B via M19. Since Q2 is set to "L" in the reset operation previously effected, Q2B is set at "H", and therefore, M19 is turned ON and Q1B is grounded via M1, M19, M20 and set to "L" so that only the lower bit Q1 of the "00" data may be read out as "H" to LATCH1 in the phase1 as shown in FIG. 4.
In the phase2, the word line potential is set to 1.2V and the upper bits Q2 of "01" data and "00" data are read out. The bit line voltage is applied to the transistor M4, Q2B of the LATCH2 is grounded by the read signal L2 input to M5 and Q2 is set to "H" so that the upper bit of the "01" data is read out as shown in FIG. 4. At this time, Q2 of the memory cell in which the "00" data is written is also set to "H".
In the phase3, the word line is set to 0V and the lower bit of "10" data is read out. The bit line voltage is applied to M1. The bit line potential is set at a high level in any case of "00", "01", "10", but since M19 is controlled by Q2B, Q1 is not inverted in the case of "01" data, Q2B is already set at "L" at this time in the case of "00" data, and only Q1 of "10" data is correctly read out by the read signal L3.
The voltages of the nodes (Q2, Q1) after the above three phases are effected are set to (L, L), (L, H), (H, L), (H, H) when the states of the selected cell are "11", "10", "01", "00" as shown on the right side of FIG. 4.
As described above, in the conventional sense/latch circuit, since "10" data is written without inhibiting the write operation of "00" data at the write time of "10" data when "10", "01", "00" are separately written in the separate phases, the write state of "10" data can be verified, but at the same time, the threshold voltage of the memory cell into which "00" data is written is shifted, and since the verify operation does not respond to the shift amount at all, there occurs a possibility that over-program of "00" data may occur in a case where the write characteristics of the memory cells in one page significantly deviate.
Further, when the threshold value of the memory cell is set to 6V or more by the over-program, no current flows even if a voltage of 6V as shown in TABLE 1 is applied to the unselected word line and there occurs a problem that a read error of information of the selected cell will occur. That is, in the NAND-type flash memory, since an over-programmed cell prevents readout of data from the cell serially connected to the same string, the above problem becomes serious in the multi-level flash memory in which the threshold value of the memory cell must be precisely controlled.
Further, in the conventional circuit, since Q1 of "00" data which lies in the same page is "L" after all of "10" data items are correctly written at the "10" verify time, for example, it is impossible to simultaneously effect the verify detection for each page unit. Therefore, a problem that the verify time becomes longer occurs since the readout operation only for Q1 of the sense/latch circuit in which "10" is loaded becomes necessary by scanning inner column address for each byte unit in the "10" verify operation.